Semiconductor devices are found in many products in the fields of entertainment, communications, networks, computers, and household markets. Semiconductor devices are also found in military, aviation, automotive, industrial controllers, and office equipment. The semiconductor devices perform a variety of electrical functions necessary for each of these applications.
The manufacture of semiconductor devices involves formation of a wafer having a plurality of die. Each semiconductor die contains hundreds or thousands of transistors and other active and passive devices performing a variety of electrical functions. For a given wafer, each die from the wafer typically performs the same electrical function. Front-end manufacturing generally refers to formation of the semiconductor devices on the wafer. The finished wafer has an active side containing the transistors and other active and passive components. Back-end manufacturing refers to cutting or singulating the finished wafer into the individual die and then packaging the die for structural support and environmental isolation.
One goal of semiconductor manufacturing is to produce a package suitable for faster, reliable, smaller, and higher-density integrated circuits (ICs) at lower cost. Flip chip packages, wafer level chip scale packages (WLCSP), and bump chip carriers (BCCs) are ideally suited for ICs demanding high speed, high density, and greater pin count. BCC packages involve mounting a die over a substrate. Contact pads formed over the active surface of the die are wirebonded to contact pads formed over the substrate. The package is then molded and singulated for addition to other systems. However, because wirebonds are used to connect the die to the substrate, the height of the BCC package is increased resulting in relatively low-density packing. Furthermore, because the package incorporates wirebonding, the manufacturing process is relatively expensive and requires an extended manufacturing process. In contrast, wafer level process interconnection methods are more efficient and cost-effective than traditional wirebonding methods. Wafer level process interconnection methods also allow for longer electrical interconnection than wirebonding, BCC or quad-flat non-leaded (QFN) packaging technologies.